1. Field of the Invention
This invention relates to a semiconductor integrated circuit, which includes a non-volatile memory capable of electrically re-writing data and used as a main memory of a microcomputer or the like for controlling an apparatus.
2. Description of the Prior Art
Recently, an EEPROM (electrically erasable and programmable read only memory) or like non-volatile memory, which does not require the back-up of the stored data and is capable of electric re-writing of data, is used as part of a main memory of a microcomputer.
FIG. 7 is a block diagram showing the construction of a prior art microcomputer. Reference numeral 1 designates a CPU (central processing unit) with a clock source 1a, 2 a non-volatile program memory consisting of a masked ROM incapable of electrically re-writing data or an EPROM capable of electrically re-writing data, 3 a volatile data memory consisting of a static RAM or the like capable of re-writing of data, 4 a non-volatile data memory consisting of an EEPROM or the like capable of electrically re-writing data, 5 an input/output port 6, a peripheral circuit such as a timer or a communication interface, and 7 a bus connecting the individual components noted above.
FIG. 8 is a block diagram showing a prior art example of a semiconductor integrated circuit consisting of a single chip provided with the non-volatile data memory 4 and a control circuit therefor or like peripheral circuit. In the Figure, reference numeral 41 designates an EEPROM consisting of an array of memory cells 41a capable of storing, for instance, 8-bit parallel data. The EEPROM has a memory capacity of several kilobytes. Numeral 42 designates an address input from an external reader/writer or CPU 1 for specifying an address of memory cells 41a of the EEPROM 41, 43 an address decoder for decoding the address input 42 and thereby selecting a memory cell 41a, 44 a data input/output terminal, through which read or write data is transferred between the EEPROM 41 and the external reader/writer or CPU 1, 45 an input/output buffer such as a tri-state buffer provided between the data input/output terminal 44 and EEPROM 41 and capable of controlling the output status of data read out from the EEPROM 41, 46 a read/write control signal input from the external reader/writer or CPU 1 for reading or writing data, and 47 a read/write controller for providing a read signal 48 for controlling the input/output buffer 45 or a write signal 49 for controlling a write line of the EEPROM 41 based on the read/write control signal 46.
The operation will now be described.
The CPU 1 reads out and executes predetermined programs from the non-volatile program memory 2. If necessary, it also performs reading or writing of data into or from the volatile or non-volatile data memory 3 or 4 and effects input or output of control data or the like through the input/output port 5. Generally, in the volatile data memory 3 the stored data vanishes when the power source is cut off. Therefore, this memory is used for an operating area of the CPU 1. In the non-volatile data memory 4, on the other hand, the stored data does not vanish even when the power source is cut off. In this memory, therefore, data requiring protection or secret data such as user's secret code is stored. The non-volatile data memory 4 is capable of reading or writing of data under control of the external reader/writer on CPU 1. This operation will be described with reference to FIG. 8.
When writing data, write data is provided from the external reader/writer or CPU 1 through the data input/output terminal and input/output buffer 45 to the EEPROM 41. Also, the address input 42 provided from the external reader/writer or CPU 1 is decoded by the address decoder 43 to select a particular row of memory cells 41a. Further, according to the read/write control signal input 46 from the external reader/writer or CPU 1, the read/write controller 47 generates a write signal 49 for the selected row of memory cells 41a, whereby data is written in a corresponding memory cell 41a.
When reading data, according to the address input 42 from the external reader/writer or CPU 1 data stored in the memory cell 41a in the row selected by the address decoder 43 is read out to be provided through an input/output buffer 45 to the external reader/writer or CPU 1. At this time, the output state of the input/output buffer 45 is controlled according to the read signal 48 from the read/write controller 47.
In the above way, data is written into or read out from a given address of the EEPROM 41.
With the above construction of the prior art semiconductor integrated circuit, data from the external reader/writer or CPU 1 can be freely written into the non-volatile data memory 4. This means that it is possible to let the external reader/writer read out a secret code or like secrete data. Therefore, it is difficult to prevent leakage of secret data to the third party. Further, a runaway of the CPU 1 due to an external disturbance or program inadequacy will permit re-writing of data requiring protection. Further, since the program memory 2 consists of a masked ROM or PROM, a program can not be readily re-writing when it is necessary to effect re-writing. To solve this problem, it is conceivable to construct the program memory with a non-volatile memory capable of re-writing of data. In this case, however, although it is possible to freely re-write data, a program is liable to be re-written due to a runaway of the CPU like the data requiring protection noted above.